Co-Design Systemsim 2.0 Adds Advanced SUPERLOG Verification for Designers, SystemVerilog Modeling

Systemsim 2.0 Testbench Capabilities Eliminate Errors Early In Flow, First With SystemVerilog, Verilog2K Simulation

LOS ALTOS, Calif.--(BUSINESS WIRE)--June 3, 2002-- Co-Design Automation, Inc., a design verification solutions provider, today released Systemsim(TM) 2.0, an upgraded simulation capability with enhanced automated testbench features, targeting the needs of hardware designers by enabling easy, effective block-level testing.

In addition, Systemsim 2.0 is the first product in the industry to support simulation of the Accellera SystemVerilog and Verilog2001 standards for concise, error-free modeling.

"Users of Verilog, including hardware designers, are desperate for a solution that will enable automatic testbench generation without the fuss and costs of learning a new, proprietary language," says Simon Davidmann, chief executive officer of Co-Design Automation. "Customer feedback convinced us that we have made a significant and powerful technological breakthrough by using Verilog-based verification to take the tedium out of block-level testing." Verification For Designers

Unifying the simulator and automated testbench capability for performance and ease of use, the Systemsim 2.0 verification mechanism now includes SystemVerilog Assertions. Combined with constrained random data generation, queuing, and object-oriented programming features, these powerful, Verilog-based capabilities enable quick block-level testing, allowing bugs to be more easily eliminated earlier in the design flow.

By driving verification algorithms with the SUPERLOG® Hardware Design and Verification Language (HDVL) components, designers are able to create effective block- level tests with relatively little coding in a familiar language. This contrasts with an older methodology of utilizing separate design and verification languages that created artificial design flow barriers. Support For Accellera SystemVerilog

Systemsim 2.0 now provides support for Accellera's SystemVerilog language standard, in addition to key Verilog2001 features, including the "generate" capability, for concise, error-free coding. SystemVerilog contains powerful language features for abstract design work with extensions for system and verification, including "interfaces" for improved communication modeling, C style programming features, assertions, and other Verilog enhancements.

Additionally, Co-Design's Systemex expander converts the syntax back to Verilog95 RTL to enable a SystemVerilog/Verilog2001 synthesis path.

This move makes Co-Design Automation the first electronic design automation (EDA) software vendor to offer this language support in products shipping today.

Co-Design has also improved CBlend(TM), its C/HDL integration capability within Systemsim 2.0. Enhancements allow Verilog and SUPERLOG code running on Systemsim to be transparently encapsulated in a C/C++/SystemC program, simplifying the mixed use of C and HDLs. The many applications of this technology include performance simulation of embedded processor based devices and the use of C or C++ for block modeling, tests, or architectural to implementation linkage.

Further performance enhancements have been added throughout the simulation algorithm, improving Verilog and SUPERLOG runtime speeds.

"Systemsim 2.0 dramatically increased the simulation performance on our production-level design with minimal setup effort," notes James Lee, technical manager at Intrinsix Corp. "The CBlend interface, coupled with the ability to leverage SUPERLOG and SystemVerilog constructs easily on top of existing Verilog designs, makes Systemsim 2.0 a natural choice for next-generation verification."

Systemsim 2.0 will be demonstrated at the 39th Design Automation Conference (DAC) in Booth Number 2360 June 10, through June 13, at the Ernest N. Morial Convention Center in New Orleans.

Pricing and Availability

Systemsim 2.0 is in use today in production environments at electronics and systems companies worldwide. It is available either as a perpetual or time-based license, starting at $18,400 per year for a three-year contract, and runs on the Sun Solaris and Linux operating systems.

Contact Dave Kelf, Co-Design's vice president of marketing, for more details or to schedule a private demonstration during DAC. He can be reached via email at davek@co-design.com or at (877) 6 CODESIGN, Ext. 404.

About Co-Design Automation

Co-Design Automation, Inc., is an EDA company focused on design verification solutions for large-scale electronic designs. It is privately held and funded by Intel Capital Corporation and Redwood Venture Partners Inc., along with investors from the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL and the first fellow at Cadence Design Systems Inc. (NASDAQ: CDN - News), and Peter Flake, creator of the HILO HDL. In 1999, Co-Design announced the SUPERLOG language, now utilized by multiple partner companies. Its products -- Systemsim and Systemex -- are achieving success throughout the electronics industry worldwide in design and verification applications. Corporate headquarters is in Los Altos, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.

SUPERLOG is a registered trademark and SYSTEMSIM, SYSTEMEX, CBlend are trademarks of Co-Design Automation, Inc. Verilog is a trademark of Cadence Design Systems, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

     Public Relations for Co-Design
     Nanette Collins
     (617) 437-1822
     nanette@nvc.com
      or
     Vice President of Marketing at Co-Design
     David Kelf
     (617) 571-9883
     davek@co-design.com